1. Field of Invention
The present invention relates to semiconductor chip packages, such as quad flat no-lead (QFN) packages and, more specifically, to a system and method for reducing pitch and increasing the lead count on such packages.
2. Description of Prior Art
An integrated chip package, such as a QFN package, comprises a plastic encapsulated semiconductor die mounted to a lead frame having a die pad and exposed outer leads on the periphery of the package. The lead frame is commonly fabricated from an electrically conductive material, such as metal, and chemically etched according to a predetermined pattern to form the leads. The pattern of lead is dictated by the use of an etching mask that is positioned against the lead frame and dictates which portions are etched away. Once the lead frame has been etched to form the leads, excess material is removed by saw singulation.
Electronic devices using such packages are constantly shrinking in size while demanding increased processing power. As faster and more powerful chips are developed, however, the I/O counts increase and a higher number of leads are required on the package. The numbers of leads that can be formed by conventional etching, however, are limited by the thickness of the lead frame material and the physical requirements for a minimum degree of spacing between leads. Thus, there is a constant need to increase the number of leads in a QFN package while reducing the space used by the leads.
One attempt to increase the number of leads on the lead frame involves the etching of double rows of leads into periphery of the lead frame. The use of additional rows, however, increases the overall footprint of the package and requires an additional saw singulation step to free the additional row from the lead frame. Previous attempts to increase the number of leads in other types of packages have involved the bonding of an additional row of leads over the top of the primary leads with an insulating adhesive. The physical bonding of additional rows, however, requires additional processing steps and may increase the overall height of the package.
3. Objects and Advantages
It is a principal object and advantage of the present invention to provide a chip package having a high number of leads that does not increase the dimensions of the package.
It is an additional object and advantage of the present invention to provide a method for forming a chip package having a high number of leads that does not require additional processing steps.
It is a further object and advantage of the present invention to provide a chip package having a high number of leads that can be fashioned from a single lead frame.
Other objects and advantages of the present invention will in part be obvious, and in part appear hereinafter.